1. Field of the Invention
The present invention relates to semiconductor devices. In particular, the present invention relates to a semiconductor device including a heterojunction bipolar transistor.
2. Description of the Related Art
A heterojunction bipolar transistor (hereinafter, referred to as a “HBT”) is a type of a bipolar transistor. The HBT includes an emitter layer composed of a material having a band gap greater than that of a base layer. Even when the base layer has an impurity concentration higher than that in the emitter layer, electron injection efficiency (emitter efficiency) from the emitter layer to the base layer can be maintained at a high level. Thus, the HBT has basic advantages in that emitter-base capacitance and base resistance can be reduced and punch-through in the base layer can be suppressed, without a decrease in current gain due to reduced emitter efficiency.
Referring to FIG. 19, a known HBT 74a as an example will be described (see Patent Document 1: Japanese Unexamined Patent Application Publication No. 7-211729, page 5, left column, line 17 to page 5, right column, line 6; and FIG. 1).
In the heterojunction bipolar transistor 74a, an n+-type GaAs subcollector layer (not shown), an n-type GaAs collector layer 53, a p-type GaAs base layer 54, an n-type AlGaAs emitter layer 55, an n+-type GaAs emitter contact layer 55b, a base electrode 65, and an emitter electrode 66 that are laminated on a semi-insulating GaAs substrate (not shown). Side faces of the emitter layer 55, the emitter contact layer 55b, and the emitter electrode 66 are covered with an insulating film 70.
The base layer on the collector layer 53 includes an intrinsic base region 54b having a carbon concentration of 1×1020 cm−3. Carbon is passivated with hydrogen; hence, hole concentration is 5 ×1019 cm−3.
An external base region (base contact region) 54c having a carbon concentration of 1×1020 cm−3 is disposed on the periphery of the surface of the base layer. Substantially 100% of carbon is activated; hence, hole concentration is 1×1020 cm−3. The emitter layer 55 is disposed on the intrinsic base region 54b so as to form a heterojunction. The base electrode 65 is in ohmic contact with the external base region 54c. 
FIG. 20 shows a heterojunction bipolar transistor 74b as another example (see Patent Document 2: Japanese Unexamined Patent Application Publication No. 5-136159, page 4, right column, line 17 to page 6, left column, lime 9; and FIG. 1).
The heterojunction bipolar transistor 74b includes a laminate containing a subcollector layer 52, a GaAs collector layer 53, a p-type AlGaAs base layer 54, an n-type AlGaAs emitter layer 55, an n-type InGaAs emitter cap layer 76, an emitter contact layer 55b, a collector electrode 67, a base electrode 65, and emitter electrode 66 disposed on a semi-insulating GaAs substrate 51.
The emitter electrode 66 composed of a nonalloy electrode material is formed in an initial step in a process for producing the HBT 74b. An emitter mesa and the base electrode 65 are formed in a self-aligned manner with respect to the emitter electrode 66. Furthermore, the base and a collector mesa are formed in a self-aligned manner with respect to the base electrode 65.
The HBT 74b has an emitter ledge structure. The base electrode 65 is formed on the extension of the lower portion of the emitter layer 55. A Pt-diffused region 73 (base contact) is formed in the lower portion to cover the surface of the base layer 54, thereby effectively preventing recombination at the surface.
Such HBTs can operate at high current and are thus satisfactory as devices for power amplifiers (hereinafter, also referred to as “PAs”). Furthermore, in recent years, the HBTs have been used for PAs for mobile communication terminals because single supply operation is advantageously easy.
Power-added efficiency (PAE) is one of the important indicators in the PA. The PAE is defined as the ratio of the difference between an output power Pout and an input power Pin to a dc input power Pdc, i.e., (Pout - Pin)/Pdc. The PAE is an indicator representing the efficiency of the PA. A large PAE results in the suppression of power consumption. In the mobile communication terminals, the power consumption of the power amplifier accounts for the major share of the total power consumption. Thus, it is particularly important to increase the PAE.
To increase the PAE, it may be necessary to minimize a knee voltage (Vk) in the relationship between the collector current (Ic) and the collector-to-emitter voltage (Vce) of the HBT. FIG. 21 is a schematic graph showing the Ic-Vce characteristics and the knee voltage (Vk). As is clear from this figure, in order to reduce the knee voltage (Vk), in the Ic-Vce characteristics, it may be necessary to minimize a voltage when Ic=0, i.e., an offset voltage (Voff), and to minimize on-resistance (Ron) when Ic starts to flow.
To reduce the Voff, it may be necessary to minimize the difference expressed as (Vbe-on)−(Vbc-on), wherein Vbe-on represents the forward turn-on voltage of an emitter-base pn junction, and Vbc-on represents the forward turn-on voltage of a base-collector pn junction. In a HBT including a type-I heterojunction, such as AlGaAs/GaAs, as an emitter-base junction, energy discontinuity occurs between conduction band edges to increase Vbe-on. For the purpose of decreasing Vbe-on, a graded sublayer for smoothly connecting band gaps is often disposed between the emitter layer and the base layer.
For example, in a HBT including a base layer and a collector layer that are composed of a semiconductor having the same composition, applying a positive voltage to the base layer results in the injection of holes from the base layer to the collector layer to increase a forward current that flows from the collector layer to the base layer, thus increasing Voff. A double heterojunction structure including a wide-band-gap semiconductor disposed at a collector side is effective in suppressing the hole injection (see Non-Patent Document 1: Applied Physics Letters, 29 Dec. 2003, Vol. 83, No. 26, pages 5545-5547).
However, also in a base-collector junction, energy discontinuity generally occurs between conduction band edges. In particular, when the collector layer has an electron affinity lower than that of the base layer, the energy discontinuity between the conduction band edges inhibits the flow of current, thereby causing the degradation of Ron. To prevent as much as possible such problems, it is known that an undoped layer that have the same composition as that of the base layer or a graded sublayer is disposed between the base layer and the collector layer.
On the other hand, in a practical HBT described in Patent Document 2, from the standpoint of reliability, in order to suppress surface recombination between an emitter layer and a base layer, the emitter layer is not completely removed but partly left in a region for forming a base electrode, in other words, an emitter ledge structure is generally formed. In this structure, the emitter-base junction is not exposed; hence, the structure is useful for the suppression of degradation in reliability due to the increase of surface defects.